The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices having output driver circuits therein.
Integrated circuit devices may contain specialized output driver circuits therein for driving external devices when the loads associated with the external devices are appreciable. Referring now to FIG. 1, an integrated circuit device may also be provided having a plurality of memory modules 111, 113, 115 and 117 therein which are electrically coupled to a data bus (DATA), a command bus (CMD) and a chip select (CS) signal line. Each memory module may itself be comprised of a plurality of memory devices 101, 103, 105 and 107. As will be understood by those skilled in the art, an increase in the number of memory modules on an integrated circuit system board may lead to unbalanced loading on the memory modules. Such unbalanced loading may be caused by the unequal lengths in the signal lines connected to the modules and may result in clock skew which limits high frequency performance.
FIG. 2 illustrates a conventional output driver circuit which comprises a PMOS pull-up transistor P1 and an NMOS pull-down transistor N1, connected as illustrated. As will be understood by those skilled in the art, application of logic 0 signals as DOKP and DOKN to the gates of the PMOS pull-up transistor P1 and NMOS pull-down transistor N1 will cause the output DOUT to be pulled to VCC. Similarly, application of logic 1 signals as DOKP and DOKN to the gates of the PMOS pull-up transistor P1 and NMOS pull-down transistor N1 will cause the output DOUT to be pulled to VSS. Finally, simultaneous application of a logic 1 signal as DOKP to the gate of the PMOS pull-up transistor P1 and a logic 0 signal as DOKN to the gate of the NMOS pull-down transistor N1 will cause the output DOUT to float in a high impedance state.
FIG. 3 illustrates another conventional output driver circuit which comprises an NMOS pull-up transistor N2 and an NMOS pull-down transistor N3, connected as illustrated. As will be understood by those skilled in the art, application of logic 1 and logic 0 signals as DOKP and DOKN, respectively, will cause the output DOUT to be pulled to VCC. Similarly, application of logic 0 and logic 1 signals as DOKP and DOKN, respectively, will cause the output DOUT to be pulled to VSS. Finally, simultaneous application of logic 0 signals as DOKP and DOKN will cause the output DOUT to float in a high impedance state.
Unfortunately, the driving capability of the circuits of FIG. 2 and 3, which is a function of the sizes of the pull-up and pull-down transistors, is fixed and typically cannot be varied in response to dynamic or static variations in loading. Thus, notwithstanding these conventional driver circuits, there continues to be a need for improved driver circuits which account for variations in loading.
It is therefore an object of the present invention to provide improved driver circuits and integrated circuit devices containing improved driver circuits therein.
It is another object of the present invention to provide driver circuits which can account for variations in loading.
These and other objects, features and advantages of the present invention are provided by output drivers which contain a plurality of driver circuits therein that are commonly connected to an output line to be driven and can be selectively enabled or disabled to increase or decrease drive capability, respectively. Driver circuits according to an embodiment of the present invention include first and second control signal lines (e.g., MRS1, MRS2), a first pull-up/pull-down driver circuit having first and second data inputs, a first control input electrically coupled to the first control signal line (e.g., MRS1) and a second control input, and a second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to the second control signal line (e.g., MRS2) and a second control input. First and second complementary control signals lines (e.g., {overscore (MRS1)}, {overscore (MRS2)}) are also preferably provided and the second control inputs of the first pull-up/pull-down driver circuit and second pull-up/pull-down driver circuit are electrically coupled to the first and second complementary control signal lines, respectively. These control signal lines and complementary control signal lines can be used to control the number of driver circuits that are active within the output driver, based on loading conditions.
According to a preferred aspect of the present invention, the first and second pull-up/pull-down driver circuits each comprise first and second PMOS transistors and first and second NMOS transistors. In particular, the first and second NMOS transistors of the first pull-up/pull-down driver circuit have respective gate electrodes which correspond to the first data input and the first control input, respectively, and the first and second PMOS transistors of the first pull-up/pull-down driver circuit have respective gate electrodes which correspond to the second data input and the second control input, respectively. Alternatively, the plurality of pull-up/pull-down driver circuits may each comprise four MOS transistors of the same type electrically connected in series between first and second supply signal lines (e.g., VCC and VSS).
According to another aspect of the present invention, a pull-up/pull-down driver circuit is provided which is always active to provide a baseline level of drive capability. In particular, a third pull-up/pull-down driver circuit may be provided which comprises only a single pair of MOS transistors and has first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively.
In addition, a controller is preferably provided which generates a first pair of complementary control signals on the first control signal line and the first complementary control signal line and generates a second pair of complementary control signals on the second control signal line and the second complementary control signal line, in response to command signals and an address. If the preferred driver circuit is used in an integrated circuit memory device, a memory array may also be provided which is electrically coupled to a pair of differential data lines and a data buffer may be provided which has first and second inputs electrically coupled to the pair of differential data lines and first and second outputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit.